1. Field of the Invention
The present invention relates to a booster circuit for obtaining a voltage higher than the power source voltage or a voltage lower than the ground potential, and more particularly to a booster circuit provided in a semiconductor chip.
2. Description of the Related Art
A semiconductor memory, e.g. a flash EEPROM (flash electrically erasable programmable read only memory) employs a voltage higher than the power source voltage or a voltage lower than the ground potential to write data into or erase data from the memory cells. FIG. 1 is a block diagram showing a write circuit of a flash EEPROM. The high voltage generated by a booster circuit 1 is fed to a data input section 2, a column decoder 3 and a row decoder 4, and data is written into memory cell 5 by injecting channel hot electrons into the floating gates.
FIG. 2A shows a conventional booster circuit, and FIG. 2B clock pulses for controlling this booster circuit. As FIG. 2B shows, to generate a high voltage within a short time, the circuit is controlled by four clock pulses. The clock pulses differ from each other in timing to prevent a decrease in voltage raising efficiency. As FIG. 2A shows, a plurality of booster units (e.g. T1, T2, C1 and C2), each consisting of first and second transistors and first and second capacitors, are connected in series. A switch block consists of a switching transistor T9 which has one current terminal connected to the output terminal of the final-stage booster unit and the other current terminal connected to the voltage output node. The gate of the transistor T9 is connected to the gate of the second transistor of the final-stage booster unit, to one terminal of the second capacitor, and to one of the current terminals of the transistor T9 itself. The aim of this arrangement is to (1) operate the final-stage booster unit and the transistor T9 in correspondence with each other; (2) to apply a high drive voltage to the gate of the transistor T9 so that sufficiently boosted current can flow; and (3) to prevent current backflow.
As FIG. 2A shows, the booster circuit has a plurality of booster sections. The booster sections are identical in structure and operation. Therefore, the operation of the first booster section only will be explained with reference to FIG. 2C, which shows the waveform of the voltage that the first booster section generates in the initial phase of its operation. As seen from FIG. 2C, the node A is charged to voltage V.sub.CC in the period (1); a current flows from the node A to the node D in the periods (2), (4) and (6); a high voltage is generated at the node D in the periods (3) and (5).
As can be seen from the above, the conventional booster circuit has a transistor T9 through which a current is output. The transistor T9 is a diode-connection transistor, in which a gate and a drain are directly connected to avoid backflow of the output current V.sub.OUT. The voltage V.sub.OUT is thus lower than the voltage generated at node L by the threshold voltage of the transistor T9, that is, by the voltage between the drain and the source. The higher the output voltage V.sub.OUT, the higher the threshold voltage of the transistor T9, and the greater the voltage loss at the transistor. Hence, the boosting ability of the circuit decreases as the rise of the output voltage. Also, the conventional booster circuit generates a high voltage only once during a certain period of one cycle of the input clock pulse. That is, high voltage and not-high voltage are generated alternately. If the booster circuit has a small output capacity, the output voltage V.sub.OUT is a pulsating one. To render the voltage V.sub.OUT non-pullsating, a smoothing capacitor may be provided at the output. A smoothing capacitor, if used, deteriorates the integration density of the memory.